Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit
نویسندگان
چکیده
منابع مشابه
Design and Performance Analysis of hybrid adders for high speed arithmetic circuit
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is bee...
متن کاملsimulation and design of electronic processing circuit for restaurants e-procurement system
the poor orientation of the restaurants toward the information technology has yet many unsolved issues in regards to the customers. one of these problems which lead the appeal list of later, and have a negative impact on the prestige of the restaurant is the case when the later does not respond on time to the customers’ needs, and which causes their dissatisfaction. this issue is really sensiti...
15 صفحه اولDesign and Synthesis of High Speed Low Power Signed Digit Adders
Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to {–1, 0, 1}, and finally adding the tra...
متن کاملDesign of High Speed 128 bit Parallel Prefix Adders
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages comp...
متن کاملDesign of High-Speed Low-Power Parallel-Prefix VLSI Adders
Parallel-prefix adders offer a highly-efficient solution to the binary addition problem. Several parallel-prefix adder topologies have been presented that exhibit various area and delay characteristics. However, no methodology has been reported so far that directly aims to the reduction of switching activity of the carry-computation unit. In this paper by reformulating the carry equations, we i...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of VLSI Design & Communication Systems
سال: 2012
ISSN: 0976-1527
DOI: 10.5121/vlsic.2012.3303